1. Field of the Invention
The present invention relates to a semiconductor process, more specifically, to a method for forming a deep trench structure and a deep trench capacitor.
2. Description of the Prior Art
Deep trench capacitors have been widely employed in the conventional semiconductor memory (such as DRAM) process, in order to reduce the occupied areas and to increase capacitances. In general, the formation of a deep trench capacitor is completed by forming a deep trench with desired depth (e.g., 7–8 μm) in a substrate once, followed by implementing some steps, including deposition, photoresist, etching, etc, several times, to form the buried plate (BP) (i.e., the bottom electrode), dielectric layer, upper electrode, collar oxide layer, connection electrode, and buried strap (BS) separately.
However, because the aforementioned deep trench process is restricted in process capability with the gradual shrinking of the dimension of components, particularly in sub-90 μm process, the etching uniformity inside the trench becomes worse, thereby influencing the overall electrical performance of the capacitors.
Therefore, a need for overcoming the above problem is required. The present invention fulfils this need.